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? semiconductor components industries, llc, 2014 october, 2016 ? rev. 10 1 publication order number: asx340at/d asx340at 1/4\inch color cmos ntsc/pal digital image soc with overlay processor general description the on semiconductor asx340at is a vga-format, single-chip cmos active-pixel digital image sensor for automotive applications. it captures high-quality color images at vga resolution and outputs ntsc or pal interlaced composite video. the vga cmos image sensor features on semiconductor?s breakthrough low-noise imaging technology that achieves superior image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low power, and integration advantages of on semiconductor?s advanced active pixel cmos process technology. the asx340at is a complete camera-on-a-chip. it incorporates sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface or by an attached spi eeprom or flash memory that contains setup information that may be loaded automatically at startup. the asx340at performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, 50hz/60hz flicker detection and avoidance, lens shading correction, auto white balance (awb), and on-the-fly defect identification and correction. the asx340at outputs interlaced-scan images at 60 or 50 fields per second, supporting both ntsc and pal video formats. the image data can be output on one or two output ports: ? composite analog video (single-ended and differential output support) ? parallel 8-, 10-bit digital features ? low-power cmos image sensor with integrated image flow processor (ifp) and video encoder ? 1/4-inch optical format, vga resolution (640 h x 480 v) ? 2x upscaling zoom and pan control ? 40 additional columns and 36 additional rows to compensate for lens alignment tolerances ? option to use single 2.8 v power supply with off-chip bypass transistor ? overlay generator for dynamic bitmap overlay ? integrated video encoder for ntsc/pal with overlay capability and 10-bit i-dac ? integrated microcontroller for flexibility ? on-chip image flow processor performs sophisticated processing, such as color recovery and correction, sharpening, gamma, lens shading correction, on-the-fly defect correction, auto white balancing, and auto exposure www.onsemi.com see detailed ordering and shipping information on page 3 of this data sheet. ordering information ibga63 7.5 7.5 case 503ae ? auto black-level calibration ? ? ? ? ? ? ? ? a pplications ? automotive rear view camera and side mirror ?
asx340at www.onsemi.com 2 table 1. key parameters parameter typical value pixel size and type 5.6 mm x 5.6 mm active pinned-photodiode with high-sensitivity mode for low-light conditions sensor clear pixels 728 h x 560 v (includes vga active pixels, demosaic and lens alignment pixels) ntsc output 720 h x 487 v pal output 720 h x 576 v optical area (clear pixels) 4.077 mm x 3.136 mm optical format 1 / 4 -inch frame rate 50/60 fields/sec sensor scan mode progressive scan color filter array rgb standard bayer chief ray angle (cra) 0 shutter type electronic rolling shutter (ers) automatic functions exposure, white balance, black level offset correction, flicker detection and avoidance, color saturation control, on the-fly defect correction, aperture correction programmable controls exposure, white balance, horizontal and vertical blanking, color, sharpness, gamma correction, lens shading correction, horizontal and vertical image flip, zoom, windowing, sampling rates, gpio control overlay support utilizes spi interface to load overlay data from external flash/eeprom memory with the following features: ? available in analog output and bt656 digital output ? overlay size 360 x 480 pixel rendered into 720 x 480 (ntsc) or 720 x 576 (pal) ? up to four (4) overlays may be blended simultaneously ? selectable readout: rotating order user-selected ? dynamic scenes by loading pre-rendered frames from external memory ? palette of 32 colors out of 64 000 ? 8 colors per bitmap ? blend factor dynamically-programmable for smooth transitions ? fast update rate of up to 30 fps ? every bitmap object has independent x/y position ? statistic engine to calibrate optical alignment ? number generator adc 10-bit, on-chip output interface analog composite video out, single-ended or differential; 8-, 10-bit parallel digital output output data formats 1 digital: raw bayer 8-,10-bit, ccir656, 565rgb, 555rgb, 444rgb data rate parallel: 27 mhz pixel clock ntsc: 60 fields/sec pal: 50 fields/sec control interface two-wire i/f for register interface plus high-level command exchange. spi port to interface to external memory to load overlay data, register settings, or firmware extensions. input clock for pll 27 mhz spi clock frequencies 1.6875 ? 18 mhz, programmable supply voltage analog: 2.8 v + 5% core: 1.8 v + 5% (2.8 v + 5% power supply with off-chip bypass transistor generates a 1.70 ? 1.95 v core voltage supply, which is acceptable for performance.) supply voltage io: 2.8 v + 5% power consumption analog output only full resolution at 60 fps: 291 mw digital output only full resolution at 60 fps: 192 mw package 63-bga, 7.5 mm x 7.5 mm, 0.65 mm pin pitch
asx340at www.onsemi.com 3 table 1. key parameters (continued) parameter typical value ambient temperature operating: ? 40 c to 105 c functional: ? 40 c to + 85 c storage: ? 50 c to + 150 c dark current < 200 e/s at 60 c with a gain of 1 fixed pattern noise column < 2 % row < 2 % responsivity 16.5 v/lux ? s at 550 nm signal to noise ratio (s/n) 46 db pixel dynamic range 87 db new features ? temperature sensor for dynamic feedback and sensor control ? automatic 50 hz/60 hz flicker detection ? 2x upscaling zoom and pan/tilt control ? independent control of colorburst parameters in the ntsc/pal encoder ? horizontal field of view adjustment between 700 and 720 pixels on the analog output ? option to use single 2.8 v power supply with off-chip bypass transistor ? spi eeprom support for lower cost system design. ordering information table 2. available part numbers part number product description orderable product attribute description asx340at2c00xped0 ? dpbr1 rev2, color, 0deg cra, ibga package drypack, protective film, anti-reflective glass asx340at2c00xped0 ? drbr1 rev2, color, 0deg cra, ibga package drypack, anti-reflective glass asx340at2c00xped0 ? tpbr rev2, color, 0deg cra, ibga package tape & reel, protective film, anti-reflective glass asx340at2c00xped0 ? trbr rev2, color, 0deg cra, ibga package tape & reel, anti-reflective glass asx340at2c00xpedd3 ? gevk rev2, color, demo kit asx340at2c00xpedh3 ? gevb rev2, color, head board asx340at3c00xped0 ? dpbr rev3, color, 0deg cra, ibga package drypack, protective film, anti-reflective glass asx340at3c00xped0 ? drbr rev3, color, 0deg cra, ibga package drypack, anti-reflective glass asx340at3c00xped0 ? tpbr rev3, color, 0deg cra, ibga package tape & reel, protective film, anti-reflective glass asx340at3c00xped0 ? trbr rev3, color, 0deg cra, ibga package tape & reel, anti-reflective glass asx340at3c00xpedd3 ? gevk rev 3, color, demo kit asx340at3c00xpedh3 ? gevb rev 3, color, head board see the on semiconductor device nomenclature document (tnd310/d) for a full description of the naming convention used for image sensors. for reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.
asx340at www.onsemi.com 4 architecture system block diagram the system block diagram will depend on the application. the system block diagram in figure 2 shows all components; optional peripheral components are highlighted. control information will be received by a microcontroller through the automotive bus to communicate with the asx340at through its two-wire serial bus. optional components will vary by application. figure 1. system block diagram spi serial data eeprom/flash 1kb ? 16mb lp filter dac _pos c 2wire i/f composite video pal /ntsc extclk system bus 2.35 k dac _ref dac _neg optional xtal 37.5 reset_bar frame _sync pixclk frame_valid line_valid ccir 656/ gpo d lsb0, 1 d [7: 0 ] v dd ( 1.8 v ) v aa (2.8 v ) v aa _pix ( 2.8 v) 2.8v v dd _io (2.8 v) v dd _pll (2.8 v) . v dd _dac (2.8 v) v reg_base 18 p f ? npo 27.000 mhz 18pf ? npo out out_
asx340at www.onsemi.com 5 internal block diagram overlay graphics generation 640 x 480 active array spi 4 2 10 2 . 8 v 1 . 8 v two ? wire i/f 8 ntsc/ pal bt ? 656 videoencoder dac image flow processor color & gama correction color space conversion edge enhancement camera control awb ae ? ??vga roi @ 60 frames per sec. spi & 2wi/f interface figure 2. internal block diagram overlay graphics generation crystal usage as an alternative to using an external oscillator, a fundamental 27 mhz crystal may be connected between extclk and xtal. two small loading capacitors of 10?22 pf of npo dielectric should be added as shown in figure 3. on semiconductor does not recommend using the crystal option for applications above 85 c. a crystal oscillator with temperature compensation is recommended. figure 3. using a crystal instead of an external oscillator extclk xtal 18 pf ? npo 27.000 mhz s ensor 18pf ? npo note: value of load capacitor is crystal dependent. crystal with small load capacitor is recommended.
asx340at www.onsemi.com 6 pin descriptions and assignments table 3. pin description pin number pin name type description clock and reset a2 extclk input master input clock (27 mhz): this can either be a square-wave generated from an oscillator (in which case the xtal input must be left unconnected) or connected directly to a crystal. b1 xtal output if extclk is connected to one pin of a crystal, this signal is connected to the other pin; otherwise this signal must be left unconnected. d2 reset_bar input asynchronous active-low reset: when asserted, the device will return all interfaces to their reset state. when released, the device will initiate the boot sequence. this signal has an internal pull-up resistor. e1 frame_sync input this input can be used to set the output timing of the asx340at to a fixed point in the frame. the input buffer associated with this input is permanently enabled. this signal must be connected to gnd if not used. register interface f1 sclk input these two signals implement the serial communications protocol for access to the internal registers and variables. f2 s data input/output e2 s addr input this signal controls the device id that will respond to serial communication commands. two-wire serial interface device id selection: 0: 0x90 1: 0xba spi interface d4 spi_sclk output clock output for interfacing to an external spi memory such as flash/eeprom. tri-state when reset_bar is asserted. e4 spi_sdi input data in from spi device. this signal has an internal pull-up resistor. h3 spi_sdo output data out to spi device. tri-state when reset_bar is asserted. h2 spi_cs_n output chip selects to spi device. tri-state when reset_bar is asserted. (parallel) pixel data output f7 frame_valid input/output pixel data from the asx340at can be routed out on this interface and processed externally. to save power, these signals are driven to a constant logic level unless the parallel pixel data output or alternate (gpio) function is enabled for these pins. this interface is disabled by default. the slew rate of these outputs is programmable. these signals can also be used as general purpose input/outputs. g7 line_valid input/output e6 pixclk output f8, d6, d7, c6, c7, b6, b7, a6 d out [7:0] output b3 d out _lsb1 input/output when the sensor core is running in bypass mode, it will generate 10 bits of output data per pixel. these two pins make the two lsb of pixel data available externally. leave d out _lsb1and d out _lsb0 unconnected if not used. to save power, these signals are driven to a constant logic level unless the sensor core is running in bypass mode or the alternate function is enabled for these pins. the slew rate of these outputs is programmable. c2 d out _lsb0 input/output
asx340at www.onsemi.com 7 table 3. pin description (continued) pin number description type pin name composite video output f5 dac_pos output positive video dac output in differential mode. video dac output in single-ended mode. this interface is enabled by default using ntsc/pal signaling. for applications where composite video output is not required, the video dac can be placed in a power-down state under software control. g5 dac_neg output negative video dac output in differential mode. a4 dac_ref output external reference resistor for the video dac. manufacturing test interface d3 tdi input jtag test pin (reserved for test mode) g2 tdo output jtag test pin (reserved for test mode) f3 tms input jtag test pin (reserved for test mode) c3 tck input jtag test pin (reserved for test mode) c4 trst_n input connect to gnd. g6 atest1 input analog test input. connect to gnd in normal operation. f6 atest2 input analog test input. connect to gnd in normal operation. gpio c1 gpio12 input/output dedicated general-purpose input/output pin. a3 gpio13 input/output dedicated general-purpose input/output pin. power g4 vreg_base supply voltage regulator control. leave floating if not used. a5, a7, d8, e7, g1, g3 v dd supply supply for v dd core: 1.8 v nominal. can be connected to the output of the transistor of the off-chip bypass transistor or an external 1.8 v power supply. b2, b8, c8, e3, e8, g8, h8 v dd_ io supply supply for digital ios: 2.8 v nominal. h5 v dd_ dac supply supply for video dac: 2.8 v nominal. a8 v dd_ pll supply supply for pll: 2.8 v nominal. b4, h6 v aa supply analog power: 2.8 v nominal. h7 v aa_ pix supply analog pixel array power: 2.8 v nominal. must be at same voltage potential as v aa . h4 reserved leave floating for normal operation. b5, c5, d1, d5, h1 d gnd supply digital ground. e5, f4 a gnd supply analog ground.
asx340at www.onsemi.com 8 pin assignments pin 1 is not populated with a ball. that allows the device to be identified by an additional marking. table 4. pin assignments 1 2 3 4 5 6 7 8 a extclk gpio13 dac_ref v dd d out 0 v dd v dd _pll b xtal v dd _io d out _lsb1 v aa gnd d out 2 d out 1 v dd _io c gpio12 d out _lsb0 tck trst_n gnd d out 4 d out 3 v dd _io d gnd reset_bar tdi spi_sclk gnd d out 6 d out 5 v dd e frame_sync s addr v dd _io spi_sdi a gnd pixclk v dd v dd _io f s clk s data tms a gnd dac_pos atest2 frame_valid d out 7 g v dd tdo v dd vreg_base dac_neg atest1 line_valid v dd _io h gnd spi_cs_n spi_sdo reserved v dd_ dac v aa v aa _pix v dd _io table 5. reset/default state of interfaces name reset state default state notes extclk clock running or stopped clock running input xtal n/a n/a input reset_bar asserted de-asserted input sclk n/a n/a input. must always be driven to high via a pull-up resistor in the range of 1.5 to 4.7 k . s data high impedance high impedance input/output. must always be driven to high via a pull-up resistor in the range of 1.5 to 4.7 k . s addr n/a n/a input. must be permanently tied to v dd _io or gnd. spi_sclk high impedance. driven, logic 0 output. output enable is r0x0032[13]. spi_sdi internal pull-up enabled. internal pull-up enabled input. internal pull-up is permanently enabled. spi_sdo high impedance driven, logic 0 output enable is r0x0032[13]. spi_cs_n high impedance driven, logic 1 output enable is r0x0032[13]. frame_valid high impedance high impedance input/output. this interface is disabled by default. input buffers (used for gpio function) powered down by default, so these pins can be left unconnected (floating). after reset, these pins are powered up, sampled, then powered down again as part of the auto-configuration mechanism. see note 2. line_valid pixclk high impedance driven, logic 0 output. this interface disabled by default. see note 1. d out 7 d out 6 d out 5 d out 4 d out 3 d out 2 d out 1 d out 0
asx340at www.onsemi.com 9 table 5. reset/default state of interfaces (continued) name notes default state reset state d out _lsb1 high impedance high impedance input/output. this interface disabled by default. input buffers (used for gpio function) powered down by default, so these pins can be left unconnected (floating). after reset, these pins are powered-up, sampled, then powered down again as part of the auto-configuration mechanism. d out _lsb0 high impedance high impedance dac_pos high impedance driven output. interface disabled by hardware reset and enabled by default when the device starts streaming. dac_neg dac_ref tdi internal pull-up enabled internal pull-up enabled input. internal pull-up means that this pin can be left unconnected (floating). tdo high impedance high impedance output. driven only during appropriate parts of the jtag shifter sequence. tms internal pull-up enabled internal pull-up enabled input. internal pull-up means that this pin can be left unconnected (floating). tck internal pull-up enabled internal pull-up enabled input. internal pull-up means that this pin can be left unconnected (floating). trst_n n/a n/a input. must always be driven to a valid logic level. must be driven to gnd for normal operation. frame_sync n/a n/a input. must always be driven to a valid logic level. must be driven to gnd if not used. gpio12 high impedance high impedance input/output. this interface disabled by default. input buffers (used for gpio function) powered down by default, so these pins can be left unconnected (floating) gpio13 high impedance high impedance input/output. this interface disabled by default. input buffers (used for gpio function) powered down by default, so these pins can be left unconnected (floating). atest1 n/a n/a must be driven to gnd for normal operation. atest2 n/a n/a must be driven to gnd for normal operation. 1. the reason for defining the default state as logic 0 rather than high impedance is this: when wired in a system (for example, on on semiconductor?s demo boards), these outputs will be connected, and the inputs to which they are connected will want to see a va lid logic level. no current drain should result from driving these to a valid logic level (unless there is a pull-up at the system level) . 2. these pads have their input circuitry powered down, but they are not output-enabled. therefore, they can be left floating but they will not drive a valid logic level to an attached device.
asx340at www.onsemi.com 10 soc description detailed architecture overview sensor core the sensor consists of a pixel array, an analog readout chain, a 10-bit adc with programmable gain and black offset, and timing and control as illustrated in figure 4. communication 10 ? bit data to ifp clock control register analog processing array timing and control adc figure 4. sensor core block diagram pixel array structure: the sensor core pixel array is configured as 728 columns by 560 rows, as shown in figure 5. figure 5. pixel array description demosaic rows demosaic rows demosaic columns demosaic columns active pixel array 640 x 480 (not to scale) pixel logical address = (727, 559) pixel logical address = (0, 0) lens alignment rows lens alignment rows lens alignment columns lens alignment columns (0, 0) (40, 36) (687, 523) black rows used internally for automatic black level adjustment are not addressed by default, but can be read out in raw output mode via a register setting. there are 728 columns by 560 rows of optically-active pixels (that is, clear pixels) that include a pixel boundary around the vga (640 x 480) image to avoid boundary effects during color interpolation and correction. among the 728 columns by 560 rows of clear pixels, there are 36 lens alignment rows on the top and bottom, and 40 lens alignment columns on the left and right; and there are 4 demosaic rows and 4 demosaic columns on each side. figure 6 illustrates the process of capturing the image. the original scene is flipped and mirrored by the sensor optics. sensor readout starts at the lower right corner. the image is presented in true orientation by the output display.
asx340at www.onsemi.com 11 figure 6. image capture example scene (front view) optics image capture image rendering start readout row by row image sensor (rear view) start rasterization display (front view) process of image gathering and image display sensor pixel array the active pixel array is 640 x 480 pixels. in addition, there are 72 rows and 80 columns for lens alignment and 8 rows and 8 columns for demosaic. figure 7. pixel color pattern detail (top right corner) black pixels column readout direction . . . ... direction r g first lens alignment pixel (64, 0) r g r g g g b g b g b b
asx340at www.onsemi.com 12 output data format: the sensor core image data are read out in progressive scan order. valid image data are surrounded by horizontal and vertical blanking, shown in figure 8. for ntsc output, the horizontal size is stretched from 640 to 720 pixels. the vertical size is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of the image field. for pal output, the horizontal size is also stretched from 640 to 720 pixels. the vertical size is 288 pixels per field. figure 8. spatial illustration on image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n ? 1 p 0,n p 2,0 p 2,1 p 2,2 .....................................p 2,n ? 1 p 2,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m ? 2,0 p m ? 2,1 .....................................p m ? 2,n ? 1 p m ? 2,n p m,0 p m,1 .....................................p m,n ? 1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image odd field horizontal blanking vertical even blanking vertical/horizontal blanking p 1,0 p 1,1 p 1,2 .....................................p 1,n ? 1 p 1,n p 3,0 p 3,1 p 3,2 .....................................p 3,n ? 1 p 3,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m ? 1,0 p m ? 1,1 .....................................p m ? 1,n ? 1 p m ? 1,n p m+1,0 p m+1,1 ..................................p m+1,n ? 1 p m+1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image even field horizontal blanking vertical odd blanking vertical/horizontal blanking
asx340at www.onsemi.com 13 image flow processor image and color processing in the asx340at are implemented as an image flow processor (ifp) coded in hardware logic. during normal operation, the embedded microcontroller will automatically adjust the operation parameters. the ifp is broken do wn into different sections, as outlined in figure 9. figure 9. color pipeline test pattern generator black color correction aperture correction (12 ? to ? 8 lookup) statistics engine color kill yuv to rgb raw data 10/12 ? bit rgb raw 10 8 ? bit rgb 8-bit yuv parallel output output interface rgb to yuv digital gain control lens shading correction defect correction, noise reduction, color interpolation mux ifp parallel output mux pixel array adc analog output mux ntsc/pal overlay control test patterns during normal operation of the asx340at, a stream of raw image data from the sensor core is continuously fed into the color pipeline. for test purposes, this stream can be replaced with a fixed image generated by a special test module in the pipeline. the module provides a selection of test patterns sufficient for basic testing of the pipeline.
asx340at www.onsemi.com 14 ntsc/pal test pattern generation there is a built-in standard eia (ntsc) and ebu (pal) color bars to support hue and color saturation characterization. each pattern consists of seven color bars (white, yellow, cyan, green, magenta, red, and blue). the y, cb and cr values for each bar are detailed in t ables 6 and 7. figure 10. color pipeline table 6. eia color bars (ntsc) nominal range white yellow cyan green magenta red blue y 16 to 235 180 162 131 112 84 65 35 cb 16 to 240 128 44 156 72 184 100 212 cr 16 to 240 128 142 44 58 198 212 114 table 7. ebu color bars (pal) nominal range white yellow cyan green magenta red blue y 16 to 235 235 162 131 112 84 65 35 cb 16 to 240 128 44 156 72 184 100 212 cr 16 to 240 128 142 44 58 198 212 114 ccir-656 format the color bar data is encoded in 656 data streams. the duration of the blanking and active video periods of the generated 656 data are summarized in tables 8 and 9. table 8. ntsc line numbers field description 1 ? 3 2 blanking 4 ? 19 1 blanking 20 ? 263 1 active video 264 ? 265 1 blanking 266 ? 282 2 blanking 283 ? 525 2 active video table 9. pal line numbers field description 1 ? 22 1 blanking 23 ? 310 1 active video
asx340at www.onsemi.com 15 table 9. pal (continued) line numbers description field 311 ? 312 1 blanking 313 ? 335 2 blanking 336 ? 623 2 active video 624 ? 625 2 blanking black level subtraction and digital gain image stream processing starts with black level subtraction and multiplication of all pixel values by a programmable digital gain. both operations can be independently set to separate values for each color channel (r, gr., gb, b). independent color channel digital gain can be adjusted with registers. independent color channel black level adjustments can also be made. if the black level subtraction produces a negative result for a particular pixel, the value of this pixel is set to 0. positional gain adjustments (pga) lenses tend to produce images whose brightness is significantly attenuated near the edges. there are also other factors causing fixed pattern signal gradients in images captured by image sensors. the cumulative result of all these factors is known as image shading. the asx340at has an embedded shading correction module that can be programmed to counter the shading effects on each individual r, gb, gr., and b color signal. the correction function the correction functions can then be applied to each pixel value to equalize the response across the image as follows: p corrected (row,co l )=p sensor (row,co l )*f(row,co l) (eq 1) where p is the pixel values and f is the color dependent correction functions for each color channel. color interpolation in the raw data stream fed by the sensor core to the ifp, each pixel is represented by a 10-bit integer number, which can be considered proportional to the pixel?s response to a one-color light stimulus, red, green, or blue, depending on the pixel?s position under the color filter array. initial data processing steps, up to and including the defect correction, preserve the one-color-per-pixel nature of the data stream, but after the defect correction it must be converted to a three-colors-per-pixel stream appropriate for standard color processing. the conversion is done by an edge-sensitive color interpolation module. the module pads the incomplete color information available for each pixel with information extracted from an appropriate set of neighboring pixels. the algorithm used to select this set and extract the information seeks the best compromise between preserving edges and filtering out high frequency noise in flat field areas. the edge threshold can be set through register settings. color correction and aperture correction to achieve good color fidelity of the ifp output, interpolated rgb values of all pixels are subjected to color correction. the ifp multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. the three components of the resulting color vector are all sums of three 10-bit numbers. since such sums can have up to 12 significant bits, the bit width of the image data stream is widened to 12 bits per color (36 bits per pixel). the color correction matrix can be either programmed by the user or automatically selected by the auto white balance (awb) algorithm implemented in the ifp. color correction should ideally produce output colors that are corrected for the spectral sensitivity and color crosstalk characteristics of the image sensor. the optimal values of the color correction matrix elements depend on those sensor characteristics and on the spectrum of light incident on the sensor. the color correction parameters can be adjusted through register settings. to increase image sharpness, a programmable 2d aperture correction (sharpening filter) is applied to color-corrected image data. the gain and threshold for 2d correction can be defined through register settings. gamma correction the asx340at includes a block for gamma correction that can adjust its shape based on brightness to enhance the performance under certain lighting conditions. two custom gamma correction tables may be uploaded corresponding to a brighter lighting condition and a darker lighting condition. at power-up, the ifp loads the two tables with default values. the final gamma correction table used depends on the brightness of the scene and takes the form of an interpolated version of the two tables. the gamma correction curve (as shown in figure 11) is implemented as a piecewise linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit output. the abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. the 8-bit ordinates are programmable through registers.
asx340at www.onsemi.com 16 figure 11. gamma correction curve input rgb, 12-bit 0 1000 2000 3000 4000 0 50 100 150 200 250 300 output rb, 8 bit 0.45 gamma correction rgb to yuv conversion for further processing, the data is converted from rgb color space to yuv color space. color kill to remove high-or low-light color artifacts, a color kill circuit is included. it affects only pixels whose luminance exceeds a certain preprogrammed threshold. the u and v values of those pixels are attenuated proportionally to the difference between their luminance and the threshold. yuv color filter as an optional processing step, noise suppression by one-dimensional low-pass filtering of y and/or uv signals is possible. a 3- or 5-tap filter can be selected for each signal. yuv-to-rgb/yuv conversion and output formatting the yuv data stream emerging from the colorpipe can either exit the color pipeline as-is or be converted before exit to an alternative yuv or rgb data format. output format and timing yuv/rgb data ordering the asx340at supports swapping ycbcr mode, as illustrated in table 10. table 10. ycbcr output data ordering mode data sequence default (no swap) cb i y i cr i y i+1 swapped cbcr cr i y i cb i y i+1 swapped yc y i cb i y i+1 cr i swapped cbcr, yc y i cr i y i+1 cb i table 11. rgb ordering in default mode mode (swap disabled) byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 565rgb odd r 7 r 6 r 5 r 4 r 3 g 7 g 6 g 5 even g 4 g 3 g 2 b 7 b 6 b 5 b 4 b 3 555rgb odd 0 r 7 r 6 r 5 r 4 r 3 g 7 g 6 even g 5 g 4 g 3 b 7 b 6 b 5 b 4 b 3 444 x rgb odd r 7 r 6 r 5 r 4 g 7 g 6 g 5 g 4 even b 7 b 6 b 5 b 4 0 0 0 0 x444rgb odd 0 0 0 0 r 7 r 6 r 5 r 4 even g 7 g 6 g 5 g 4 b 7 b 6 b 5 b 4
asx340at www.onsemi.com 17 uncompressed 10-bit bypass output raw 10-bit bayer data from the sensor core can be output in bypass mode in two ways: ? using 8 data output signals (d out [7:0]) and gpio[1:0]. the gpio signals are the least significant 2 bits of data. ? using only 8 signals (d out [7:0]) and a special 8 + 2 data format, shown in table 12. table 12. 2-byte bayer format byte bits used bit sequence odd bytes 8 data bits d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 d 1 d 0 readout formats progressive format is used for raw bayer output. output formats itu-r bt.656 and rgb output: theasx340at can output processed video as a standard itu-r bt.656 (ccir656) stream, an rgb stream, or as unprocessed bayer data. the itu-r bt.656 stream contains ycbcr 4:2:2 data with embedded synchronization codes. this output is typically suitable for subsequent display by standard video equipment or jpeg/mpeg compression. colorpipe data (pre-lens correction and overlay) can also be output in ycbcr 4:2:2 and a variety of rgb formats in 640 by 480 progressive format in conjunction with line_valid and frame_valid. the asx340at can be configured to output 16-bit rgb (565rgb), 15-bit rgb (555rgb), and two types of 12-bit rgb (444rgb). refer to t able 23 and t able 24 for details. bayer output: unprocessed bayer data are generated when bypassing the ifp completely ? that is, by simply outputting the sensor bayer stream as usual, using frame_valid, line_valid, and pixclk to time the data. this mode is called sensor bypass mode. output ports composite video output: the composite video output dac is external-resistor-programmable and supports both single-ended and differential output . the dac is driven by the on-chip video encoder output. parallel output: parallel output uses either 8-bit or 10-bit output. eight-bit output is used for itu-r bt.656 and rgb output. ten-bit output is used for raw bayer output. zoom support the asx340at supports zoom x1 and x2 modes, in interlaced and progressive scan modes. the progressive support is limited to the vga at either 60 fps or 50 fps. in the zoom x2 modes, the sensor is configured for qvga (320 x 240), and the zoom x2 window can be configured to pan around the vga window. fov stretch support the asx340at supports the ability to control the active ?width? of the tv output line, between 692 and 720 pixels. the hardware supports two margins, each a maximum of 14 pixels width, and has to be an even number of pixels.
asx340at www.onsemi.com 18 system configuration and usage modes how a camera based on the asx340at will be configured depends on what features are used. there are essentially three configuration modes for asx340at: auto-config mode, flash-config mode, and host-config mode. refer to system configuration and usage figure 12. analog out asx340at auto-config mode digital out figure 13. asx340at spi serial eeprom/flash figure 14. external device asx340at spi serial eeprom/flash figure 15. system bus two ? wire spi asx340at serial eeprom/flash 8/16 bit c figure 16. asx340at system bus two ? wire 8/16 bit c multicamera support two or more asx340at sensors may be synchronized to a frame by asserting the frame_sync signal. at that point, the sensor and video encoder will reset without affecting any register settings. the asx340at may be triggered to be synchronized with another asx340at or an external event. figure 17. multicamera system block diagram decoder/dsp camera 1 camera 2 cvbs cvbs system bus c asx340 asx340 f_sync osc dual camera 1 f_sync
asx340at www.onsemi.com 19 external signal processing an external signal processor can take data from itu656 or raw bayer output format and post-process or compress the data in various formats. figure 18. external signal processing block diagram spi 1kb to 16mb 27 mhz video_p extclk video_n d signal processor device configuration after power is applied and the device is out of reset by de-asserting the reset_bar pin, it will enter a boot sequence to configure its operating mode. there are essentially three three configuration modes: flash/eeprom config, auto config, and host config. figure 14: ?power-up sequence ? configuration options flow chart,? contains more details on the configuration options. the soc firmware supports a system configuration phase at start-up. this consists of five modes of execution: 1. flash detection 2. flash-config 3. auto-config 4. host-config 5. change-config (commences streaming ? completes the system configuration mode). the system configuration phase is entered immediately after the firmware initializes following soc power-up or reset. by default, the firmware first enters the flash detection mode. the flash detection mode attempts to detect the presence of an spi flash or eeprom device: ? if no device is detected, the firmware then samples the spi_sdi pin state to determine the next mode: ? if spi_sdi = 0 then it enters the host-config mode. ? if spi_sdi = 1 then it enters the auto-config mode. ? if a device is detected, the firmware switches to the flash-config mode. in the flash-config phase, the firmware interrogates the device to determine if it contains valid configuration records: ? if no records are detected, then the firmware enters the auto-config mode. ? if records are detected, the firmware processes them. by default, when all flash records are processed the firmware switches to the host-config mode. however, the records encoded into the flash can optionally be used to instruct the firmware to proceed to one of the other mode (auto-config/change-config). the auto-config mode uses the frame_valid, line_valid, d out _lsb0 and d out _lsb1 pins to configure the operation of the device, such as video format and pedestal (refer to the developer guide for more details). after auto-config completes the firmware switches to the change-config mode. in the host-config mode, the firmware performs no configuration, and remains idle waiting for configuration and commands from the host. the system configuration phase is effectively complete and the soc will take no actions until the host issues commands. in the change-config mode, the firmware performs a ?change-config? operation. this applies the current configuration settings to the soc, and commences streaming. this completes the system configuration phase.
asx340at www.onsemi.com 20 power sequence in power-up, refer to the power-up sequence in figure 44: ?power up sequence.? in power down, refer to figure 45: ?power down sequence?, for details.modes in the developer guide document for details. d out _lsb0 power up/reset auto configuration frame _ valid line_valid spi_sdi = 0? wait for host command wait for host command parse eeprom/flash content wait for host command yes no disable auto ? config host config d out _lsb1 eeprom/flash contents valid? eeprom/flash device present? no change config (default) : (optional) auto ? config change ? config auto ? config change ? config no yes figure 19. power-up sequence ? configuration options flow chart supported nvm devices the asx340at supports a variety of spi non-volatile memory (nvm) devices. refer to flash/eeprom programming section in developer guide document for details. table 13. spi flash devices type density manufacturer device speed (mhz) standard temp range (5c) supported flash 1 mb st m25p10 ? avmb3 50 ?40 to +125 yes flash 8 mb atmel at26df081a 70 jedec/device id ?20 to +85 yes eeprom 1 mb st m95m01 ? r 5 ?40 to +130 yes eeprom 8 kb microchip 25lc080 2 ?40 to +125 yes
asx340at www.onsemi.com 21 table 14. spi commands supported command value read array 0x03 block erase 0 x d8 chip erase 0 x c7 read status 0 x 05 write status 0 x 01 byte page program 0 x 02 write enable 0 x 06 write disable 0 x 04 read manufacturer and device id 0 x 9f (fast) read array 0 x 0b table 15. gpio bit descriptions gpio[11] (dout_lsb1) gpio[10] (dout_lsb0) gpio[9] (frame_valid gpi[8] (line_vali low (?0?) normal ntsc normal no pedestal high (?1?) vertical flip pal horizontal mirror pedestal host command interface on semiconductor sensors and socs contain numerous registers that are accessed through a two-wire interface with speeds up to 400 khz. the asx340at in addition to writing or reading straight to/from registers or firmware variables, has a mechanism to write higher level commands, the host command interface (hci). once a command has been written through the hci, it will be executed by on-chip firmware and the results are reported back. in general, registers should not be accessed with the exception of registers that are marked for ?user access.? eeprom or flash memory is also available to store commands for later execution. under dma control, a command is written into the soc and executed. for a complete description of host commands, refer to the asx340at host command interface specification.
asx340at www.onsemi.com 22 host command to fw response from fw 15 0 bit 1 0 command register addr 0x40 addr 0xfc00 addr 0xfc0e addr 0xfc02 addr 0xfc04 addr 0xfc06 addr 0xfc08 addr 0xfc0a addr 0xfc0c 14 door bell 15 0 bit parameter 0 parameter 7 cmd_handler_params_pool_0 cmd_handler_params_pool_3 cmd_handler_params_pool_4 cmd_handler_params_pool_5 cmd_handler_params_pool_1 cmd_handler_params_pool_2 cmd_handler_params_pool_6 cmd_handler_params_pool_7 figure 20. interface structure
asx340at www.onsemi.com 23 host command process flow figure 21. interface structure read command register doorbell bit clear ? no command has parameters ? yes write parameters yes write command no host could insert an optional delay here host could insert an optional delay here wait for a response? read command register doorbell bit clear ? yes no parameters ? yes parameter pool yes contains response code done no no at this point command register issue command to parameter pool to command register read response parameters from command has response command flow the host issues a command by writing (through a two-wire interface bus) to the command register. all commands are encoded with bit 15 set, which automatically generates the host command (doorbell) interrupt to the microprocessor. assuming initial conditions, the host first writes the command para meters (if any) to the parameters pool (in the command handler?s logical page), then writes the command to command register. the firmware interrupt handler then signals the command handler task to process the command. if the host wishes to determine the outcome of the command, it must poll the command register waiting for the doorbell bit to be cleared. this indicates that the firmware completed processing the command. when the doorbell bit is cleared, the contents of the command register indicate the command?s result status. if the command generated response parameters, the host can now retrieve these from the parameters pool. notes: the host must not write to the parameters pool, nor issue another command, until the previous command completes. this is true even if the host does not care about the result of the previous command. therefore, the host must always poll the command register to determine the state of the doorbell bit, and ensure the bit is cleared before issuing a command. for a complete command list and further information consult the host command interface specification. an example of how (using devware) a command may be initiated in the form of a ?preset? follows.
asx340at www.onsemi.com 24 issue the sysmgr_set_state command all devware presets supplied by on semiconductor poll and test the doorbell bit after issuing the command. therefore there is no need to check if the doorbell bit is clear before issuing the next command. # set the desired next state in the parameters pool(sys_state_enter_config_change) reg= 0xfc00, 0x2800 // cmd_handler_params_pool_0 # issue the hc_sysmgr_set_state command reg= 0x0040, 0x8100 // command_register # wait for the fw to complete the command (clear the doorbell bit) poll_field= command_register, doorbell,!=0, delay=10, timeout=100 # check the command was successful error_if= command_register, host_command,!=0, ?set state command failed?, summary of host commands table13 through table 21 show summaries of the host commands. the commands are divided into the following sections: ? system manager ? overlay ? gpio ? flash manager ? sequencer ? patch loader ? miscellaneous ? calibration stats following is a summary of the host interface commands. the description gives a quick orientation. the ?type? column shows if it is an asynchronous or synchronous command. for a complete list of all commands including parameters, consult the host command interface specification document. table 16. system manager commands system manager host command value type description set state 0x8100 synchronous request the system enter a new state get state 0x8101 synchronous get the current state of the system table 17. overlay host commands overlay host command value type description enable overlay 0x8200 synchronous enable or disable the overlay subsystem get overlay state 0x8201 synchronous retrieve the state of the overlay subsystem set calibration 0x8202 synchronous set the calibration offset set bitmap property 0x8203 synchronous set a property of a bitmap get bitmap property 0x8204 synchronous get a property of a bitmap set string property 0x8205 synchronous set a property of a character string load buffer 0x8206 asynchronous load an overlay buffer with a bitmap (from flash) load status 0x8207 synchronous retrieve status of an active load buffer operation write buffer 0x8208 synchronous write directly to an overlay buffer read buffer 0x8209 synchronous read directly from an overlay buffer enable layer 0x820a synchronous enable or disable an overlay layer get layer status 0x820b synchronous retrieve the status of an overlay layer set string 0x820c synchronous set the character string
asx340at www.onsemi.com 25 table 17. overlay host commands (continued) overlay host command description type value get string 0x820d synchronous get the current character string load string 0x820e asynchronous load a character string (from flash) table 18. gpio host commands gpio host command value type description set gpio property 0x8400 synchronous set a property of one or more gpio pins get gpio property 0x8401 synchronous retrieve a property of a gpio pin set gpo state 0x8402 synchronous set the state of a gpo pin or pins get gpio state 0x8403 synchronous get the state of a gpi pin or pins set gpi association 0x8404 synchronous associate a gpi pin state with a command sequence stored in spi flash get gpi association 0x8405 synchronous retrieve an gpio pin association table 19. flash manager host commands flash manager host command value type description get lock 0x8500 asynchronous request the flash manager access lock lock status 0x8501 synchronous retrieve the status of the access lock request release lock 0x8502 synchronous release the flash manager access lock config 0x8503 synchronous configure the flash manager and underlying spi flash subsystem read 0x8504 asynchronous read data from the spi flash write 0x8505 asynchronous write data to the spi flash erase block 0x8506 asynchronous erase a block of data from the spi flash erase device 0x8507 asynchronous erase the spi flash device query device 0x8508 asynchronous query device-specific information status 0x8509 synchronous obtain status of current asynchronous operation config device 0x850a synchronous configure the attached spi nvm device table 20. sequencer host commands flash manager host command value type description refresh 0x8606 synchronous refresh the automatic image processing algorithm configuration refresh status 0x8607 synchronous retrieve the status of the last refresh operation
asx340at www.onsemi.com 26 table 21. patch loader host commands patch loader host command value type description load patch 0x8700 asynchronous load a patch from spi flash and automatically apply status 0x8701 synchronous get status of an active load patch or apply patch request apply patch 0x8702 asynchronous apply a patch (already located in patch ram) reserve ram 0x8706 synchronous reserve ram to contain a patch table 22. miscellaneous host commands miscellaneous host command value type description invoke command seq 0x8900 synchronous invoke a sequence of commands stored in nvm config command seq processor 0x8901 synchronous configures the command sequencer processor wait for event 0x8902 synchronous wait for a system event to be signalled table 23. calibration stats host commands calibration stats host command value type description control 0x8b00 asynchronous start statistics gathering read 0x8b01 synchronous read the results back slave two-wire serial interface the two-wire serial interface bus enables read/write access to control and status registers within the asx340at. this interface is designed to be compatible with the mipi alliance standard for camera serial interface 2 (csi-2) 1.0, which uses the electrical characteristics and transfer protocols of the two-wire serial interface specification. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device. the master generates a clock (s clk ) that is an input to the sensor and used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). s data is pulled up to v dd_ io off-chip by a pull-up resistor in the range of 1.5 to 4.7 k . protocol data transfers on the two-wire serial interface bus are performed by a sequence of low-level protocol elements, as follows: ? a start or restart condition ? a slave address/data direction byte ? a 16-bit register address ? an acknowledge or a no-acknowledge bit ? data bytes ? a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. the s addr pin is used to select between two different addresses in case of conflict with another device. if s addr is low, the slave address is 0 x 90; if s addr is high, the slave address is 0 x ba. see table 21. table 24. two-wire interface id address switching s addr two-wire interface address id 0 0x90 1 0xba start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a ?repeated start? or ?restart? condition.
asx340at www.onsemi.com 27 data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/data direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the asx340at are 0 x 90 (write address) and 0 x 91 (read address). alternate slave addresses of 0 x ba (write address) and 0 x bb (read address) can be selected by asserting the s addr input signal. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. the protocol used is outside the scope of the two-wire serial interface specification. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowledge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transfer. a no-acknowledge bit is used to terminate a read sequence. stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. typical operation a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a write, the master then transfers the 16-bit register address to which a write will take place. this transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. the master will then transfer the 16-bit data, as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. the master stops writing by generating a (re)start or stop condition. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the master generates an acknowledge bit after each 8-bit transfer. the data transfer is stopped when the master sends a no-acknowledge bit. single read from random location figure 17 shows the typical read cycle of the host to the asx340at. the first two bytes sent by the host are an internal 16-bit register address. the following 2-byte read cycle sends the contents of the registers to host. s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data [15:8] p previous reg address, n reg address, m m+1 a read data [7:0] a figure 22. single read from random location
asx340at www.onsemi.com 28 single read from current location figure 18 shows the single read cycle without writing the address. the internal address will use the previous address value written to the register. figure 23. single read from current location slave address 1 s a read data [15:8] slave address a 1 s p read data [15:8] p previous reg address, n reg address, n+1 n+2 a a read data [7:0] a read data [7:0] a sequential read, start from random location this sequence (figure 21) starts in the same way as the single read from random location (figure 17). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 24. sequential read, start from random location read data (15:8) a a read data (15:8) a read data (7:0) a slave address 0 s sr a reg address[15:8] a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+ 1 m+3 a 1 m+l ? 2 m+l ? 1 m+l a p a read data (15:8) a read data (7:0) a read data (15:8) a read data (7:0) a read data (7:0) sequential read, start from current location this sequence (figure 20) starts in the same way as the single read from current location (figure 18). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 25. sequential read, start from current location a previous reg addr ess, n n+1 n+2 n+l ? 1 n+l a read data slave address a 1 a s p read data (15:8) a read data (7:0) a read data (15:8) a read data (7:0) a read data (15:8) a read data (7:0) a read data read data (15:8) a read data (7:0) single write to random location figure 21 shows the typical write cycle from the host to the asx340at.the first 2 bytes indicate a 16 ? bit address of the internal registers with most ? significant byte first. the following 2 bytes indicate the 16 ? bit data. figure 26. single write to random location slave address 0 s a reg add ress[15:8] a reg add ress[7:0] a p previous reg address, n reg address, m m+1 a a wri te data
asx340at www.onsemi.com 29 sequential write, start at random location this sequence (figure 22) starts in the same way as the single write to random location (figure 21). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been written. the write is terminated by the master generating a stop condition. figure 27. single write to random location slave address 0 s a reg address[15:8] a reg address[7:0] a write data previous reg address, n reg address, m m+1 m+2 m+1 m+3 a aa write data write data m+l ? 2 m+l ? 1 m+l a a p write data (15:8) write data (7:0) write data (15:8) a write data (7:0) a a a write data a write data (15:8) a write data (7:0) a write data write data (15:8) a write data (7:0) overlay capability figure 23 highlights the graphical overlay data flow of theasx340at. the images are separated to fit into 2 kb blocks of memory after compression. ? up to four overlays may be blended simultaneously ? overlay size 360 x 480 pixels rendered into a display area of 720 x 480 pixels (ntsc) or 720 x 576 (pal) ? selectable readout: rotating order is user programmable ? dynamic movement through predefined overlay images ? palette of 32 colors out of 64,000 with eight colors per bitmap ? blend factors may be changed dynamically to achieve smooth transitions the host commands allow a bitmap to be written piecemeal to a memory buffer through the two-wire serial interface, and also through dma direct from spi flash memory. multiple encoding passes may be required to fit an image into a 2 kb block of memory; alternatively, the image can be divided into two or more blocks to make the image fit. every graphic image may be positioned in the horizontal and vertical direction and overlap with other graphic images. the host may load an image at any time. under control of dma assist, data are transferred to the off-screen buffer in compressed form. this assures that no display data are corrupted during the replenishment of the four active overlay buffers.
asx340at www.onsemi.com 30 off-screen buffer overlay buffers: 2kb each decompress blend and overlay flash bitmaps ? compressed note: these images are not actually rendered, but show conceptual objects and object blending. figure 28. overlay data flow nvm partition the contents of the flash/eeprom memory partition logically into three blocks (see figure 24): ? memory for overlay data and descriptors ? memory for register settings, which may be loaded at boot-up ? firmware extensions or software patches; in addition to the on-chip firmware, extensions reside in this block of memory these blocks are not necessarily contiguous. s/w patch alternate reg. overlay data 1 2 byte head er r l e enc o d ed k byte overlay data software patch 12 ? byte header rle encoded data 2kb lens shading alternate register setting correction parameter flash partitioning overlays ? rle fixed ? size ee overlays ? rle fixed ? size figure 29. memory partitioning
asx340at www.onsemi.com 31 external memory speed requirement for a 2 kb block of overlay to be transferred within a frame time to achieve maxim um update rate, the spi nvm must operate at a certain minimum speed. table 25. transfer time estimate value type description 33.3ms 4.5 mhz 1ms overlay adjustment to ensure a correct position of the overlay to compensate for assembly deviation, the overlay can be adjusted with assistance from the overlay statistics engine: ? the overlay statistics engine supports a windowed 8-bin luma histogram, either row-wise (vertical) or column-wise (horizontal). ? the calibration statistics can be used to perform an automatic successive-approximation search of a cross-hair target within the scene. ? on the first frame, the firmware performs a coarse horizontal search, followed by a coarse vertical search in the second frame. ? in subsequent frames, the firmware reduces the region-of-interest of the search to the histogram bins containing the greatest accumulator values, thereby refining the search. ? the resultant row and column location of the cross-hair target can be used to assign a calibration value to offset selected overlay graphic image positions within the output image. ? the calibration statistics patch also supports a manual mode, which allows the host to access the raw accumulator values directly. figure 30. overlay calibration
asx340at www.onsemi.com 32 the position of the target will be used to determine the calibration value that shifts the row and column position of adjustable overlay graphics. the overlay calibration is intended to be applied on a device by device basis ?in system,? which means after the camera has been installed. on semiconductor provides basic programming scripts that may reside in the spi flash memory to assist in this effort. overlay character generator in addition to the four overlay layers, a fifth layer exists for a character generator overlay string. there are a total of: ? 16 alphanumeric characters available ? 22 characters maximum per line ? 16 x 32 pixels with 1-bit color depth any update to the character generator string requires the string to be passed in its entirety with the host command. character strings have their own control properties aside from the overlay bitmap properties. overlay layer0 layer1 layer2 layer3 bt656 bt656 timing control user registers data bus dma/cpu register bus rom figure 31. internal block diagram overlay
asx340at www.onsemi.com 33 character generator the character generator can be seen as the fifth top layer, but instead of getting the source from rle data in the memory buffers, it has 16 predefined characters stored in rom. all the characters are 1-bit depth color and are sharing the same ycbcr look up table. 0x00 0x02 0x04 0x06 0x08 0x0a 0x0c 0x0e 0x10 0x12 0x14 0x16 0x18 0x1a 0x1c 0x1e 0x20 0x22 0x24 0x26 0x28 0x2a 0x2c 0x2e 0x30 0x32 0x34 0x36 0x38 0x3a 0x3c 0x3e figure 32. example of character descriptor 0 stored in rom 0000 00 000 000 0000 0000 00 000 000 0000 0000 00 111 100 0000 0000 01 111 110 0000 0000 11 111 111 0000 0001 11 100 111 1000 0001 11 000 011 1100 0011 11 000 001 1100 0011 10 000 001 1 00 0011 10 000 001 1110 0111 10 000 000 1110 0111 00 000 000 1110 0111 00 000 000 1110 0111 00 000 000 1110 0111 00 000 000 1110 0111 00 000 000 1110 0111 00 000 000 1110 0111 00 000 000 1110 0111 00 000 000 1110 0111 00 000 000 1110 0011 10 000 000 1110 0011 10 000 001 1110 0011 10 000 001 1100 0011 11 000 001 1100 0001 11 000 011 1000 0001 11 100 111 1000 0000 11 111 111 0000 0000 01 111 110 0000 0000 00 111 100 0000 0000 00 000 000 0000 0000 00 000 000 0000 0000 00 000 000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rom it can show a row of up to 22 characters of 16 x 32 pixels resolution (32 x 32 pixels when blended with the bt 656 data). character generator details table 26. character generator details item quantity description 16-bit character 22 code for one of these characters: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /, (space), :, ?, (comma), (period) 1 bpp color 1 depth of the bit map is 1 bpp it is the responsibility of the user to set up proper values in the character positioning to fit them in the same row (that is one of the reasons that 22 is the maximum number of characters). notes: no error is generated if the character row overruns the horizontal or vertical limits of the frame.
asx340at www.onsemi.com 34 full character set for overlay figure 28 shows all of the characters that can be generated by the asx340at. 0x0 0x4 0x8 0xc 0x1 0x5 0x9 0x2 0x3 0x6 0x7 0xa 0xb 0xd 0xe 0xf figure 33. full character set for overlay modes and timing this section provides an overview of the typical usage modes and related timing information for the asx340at. composite video output the external pin d out _lsb0 can be used to configure the device for default ntsc or pal operation (auto-config mode). this and other video configuration settings are available as register settings accessible through the serial interface. ntsc both differential and single-ended connections of the full ntsc format are supported. the differential connection that uses two output lines is used for low noise or long distance applications. the single-ended connection is used for pcb tracks and screened cable where noise is not a concern. the ntsc format has three black lines at the bottom of each image for padding (which most lcds do not display). pa l the pal format is supported with 576 active image rows. single-ended and differential composite output the composite output can be operated in a single-ended or differential mode by simply changing the external resistor configuration. refer to the developer guide for configuration options. parallel output (d out ) the d out [7:0] port supports both progressive and interlaced mode. progressive mode (with fv and lv signal) include raw bayer(8 or 10 bit), ycbcr, rgb. interlaced mode is ccir656 compliant. figure 29 shows the data that is output on the parallel port for ccir656. both ntsc and pal formats are displayed. the blue values in figure 29 represent ntsc (525/60). the red values represent pal (625/50).
asx340at www.onsemi.com 35 f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r y c b y c r y c r y f f 4 4 268 280 4 4 1440 1440 eav code blanking sav code co ? sited _ co ? sited _ start of digital line start of digital active line n digital video stream figure 34. ccir656 8-bit parallel interface format for 525/60 (625/50) video systems figure 30 shows detailed vertical blanking information for ntsc timing. table 24 for data on field, vertical blanking, eav, and sav states. figure 35. typical ccir656 vertical blanking intervals for 525/60 video system blanking field 1 active vi deo blanking field 2 active vi deo line 4 266 field 1 (f = 0) odd field 2 (f = 1) even eav sav line 1 (v = 1) line 20 (v = 0) line 26 4 (v = 1) line 2 83 (v = 0) line 525 (v = 0) h = 1 h = 0 table 27. field, vertical blanking, eav, and sav states 525/60 video system line number f v h (eav) h (sav) 1?3 1 1 1 0 4?9 0 1 1 0 20?263 0 0 1 0 264?265 0 1 1 0 266?282 1 1 1 0 283?525 1 0 1 0 1. ntsc defines active video from line 20 to line 263 (corresponding to a field). this allows up to 244 active video lines in a field. 2. asx340 image output is configured to 240 lines per field; this is common practice of digital video formatting. 3. when 240 lines are displayed within a field of 244 lines, the image content should start from line 22 to line 261 of the field. this ensures center of the image and the center of the field is aligned. 4. similar consideration applies to odd & even fields.
asx340at www.onsemi.com 36 figure 31 shows detailed vertical blanking information for pal timing. see table 25 for data on field, vertical blanking, eav, and sav states. figure 36. typical ccir656 vertical blanking intervals for 625/50 video system blanking field 1 active video blanking field 2 active vi deo field 1 (f = 0) odd field 2 (f = n h = h = blanking line 1 (v = 1) line 2 3 (v = 0) line 311 (v = 1) line 336 (v = 0) line 625 (v = 1) line 62 4 (v = 1) table 28. field, vertical blanking, eav, and sav states for 625/50 video system line number f v h (eav) h (sav) 1?22 0 1 1 0 23?310 0 0 1 0 311?312 0 1 1 0 313?335 1 1 1 0 336?623 1 0 1 0 624?625 1 1 1 0 reset and clocks reset power-up reset is asserted or de-asserted with the reset_bar pin, which is active low. in the reset state, all control registers are set to default values. see ?device configuration? for more details on auto, host, and flash configurations. soft res et is asserted or de-asserted by the two-wire serial interface. in soft-reset mode, the two-wire serial interface and the register bus are still running. all control registers are reset using default values. clocks the asx340at has two primary clocks: ? a master clock coming from the extclk signal. ? in default mode, a pixel clock (pixclk) running at 2 * extclk. in raw bayer bypass mode, pixclk runs at the same frequency as extclk. when the asx340at operates in raw bayer bypass mode, the image flow pipeline clocks can be shut off to conserve power. the sensor core is a master in the system. the sensor core frame rate defines the overall image flow pipeline frame rate. horizontal blanking and vertical blanking are influenced by the sensor configuration, and are also a function of certain image flow pipeline functions. the relationship of the primary clocks is depicted in figure 32.
asx340at www.onsemi.com 37 the image flow pipeline typically generates up to 16 bits per pixel ? for example, ycbcr or 565rgb ? but has only an 8-bit port through which to communicate this pixel data. to generate ntsc or pal format images, the sensor core requires a 27 mhz clock. 10 bits/pixel 1 pixel/clock 16 bits/pixel 1 pixel/clock 16 bits/pixel (typ) 0.5 pixel/clock colorpipe output interface extclk sensor core sensor pixel clock sensor master clock figure 37. primary clock relationships floating inputs the following asx340at pins cannot be floated: ? s data? this pin is bidirectional and should not be floated ? frame_sync ? trst_n ? s clk ? s addr ? atest1 ? atest2 output data ordering table 29. eia color bars (ntsc) mode (swap disabled) byte d7 d6 d5 d4 d3 d2 d1 d0 565rgb first r7 r6 r5 r4 r3 g7 g6 g5 second g4 g3 g2 b7 b6 b5 b4 b3 555rgb first 0 r7 r6 r5 r4 r3 g7 g6 second g5 g4 g3 b7 b6 b5 b4 b3 444xrgb first r7 r6 r5 r4 g7 g6 g5 g4 second b7 b6 b5 b4 0 0 0 0 x444rgb first 0 0 0 0 r7 r6 r5 r4 second g7 g6 g5 g4 b7 b6 b5 b4 1. pixclk is 54 mhz when extclk is 27 mhz. table 30. eia color bars (ntsc) mode d7 d6 d5 d4 d3 d2 d1 d0 d out _lsb1 d out _lsb0 10-bit output b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1. pixclk is 27 mhz when extclk is 27 mhz.
asx340at www.onsemi.com 38 i/o circuitry figure 33 illustrates typical circuitry used for each input, output, or i/o pad. vd d _io receiver input pad pad gnd v dd_io receiver spi_sdi and reset_bar input pad pad gnd receiver gnd v dd_io pad i/o pad slew rate control v dd_io receiver sclk and xtal_in input pad pad gnd gnd xtal output pad dd_io note: all i/o circuitry shown above is for reference only. the actual implementation may be different. figure 38. typical i/o equivalent circuits
asx340at www.onsemi.com 39 note: all i/o circuitry shown above is for reference only. the actual implementation may be different. figure 39. ntsc block pad v dd_ dac gnd pad pad esd esd dac_ref esd dac_pos dac_neg ntsc block resistor 2.35 k figure 40. serial interface pad transmitter gnd receiver vdd_i0 sdata input/output pad i/o timing digital output by default, the asx340at launches pixel data, fv, and lv synchronously with the falling edge of pixclk. the expectation is that the user captures data, fv, and lv using the rising edge of pixclk. the timing diagram is shown in. as an option, the polarity of the pixclk can be inverted from the default by programming r0x0016[14]. extclk pixclk d out [7:0] frame_valid line_valid t pixclkf_dout t pixclkf_fvlv input output output output t fvlv_su t fvlv_ho t dout_ho t dout_su t extclk_period figure 41. digital output i/o timing
asx340at www.onsemi.com 40 table 31. parallel digital output i/o timing ( f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v; default slew rate) signal parameter conditions min typ max unit extclk f extclk 6 27 54 mhz t extclk_period 18.52 37 166.67 ns extclk duty cycle 45 50 55 % pixclk 1 f pixclk 6 27 54 mhz t pixclk_period 18.52 37.04 166.67 ns duty cycle 45 50 55 % data[7:0] t pixclkf_dout 1.55 ? 1.9 ns t dout_su 18 ? 20 ns t dout_ho 18 ? 20 ns fv/lv t pixclkf_fvlv 1.6 ? 3.05 ns t fvlv_su 15 ? 16 ns t fvlv_ho 20 ? 21 ns table 32. slew rate for poxclk and d out ( f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8 v; v aa = 2.8 v; vaa_pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v; t = 25 c; c load = 40 pf) pixclk d out [7:0] unit r0x1e [10:8] rise time fall time r0x1e [2:0] rise time fall time 000 na na 000 15.0 13.5 ns 001 na na 001 9.0 8.5 ns 010 7.0 6.9 010 6.8 6.0 ns 011 5.2 5.0 011 5.2 4.8 ns 100 4.0 3.8 100 3.8 3.5 ns 101 3.0 2.8 101 3.3 3.3 ns 110 2.4 2.2 110 3.0 3.0 ns 111 1.9 1.7 111 2.8 2.8 ns figure 42. slew rate timing 90% 10% t rise t fall pixclk d out t rise t fall
asx340at www.onsemi.com 41 configuration timing during start-up, the dout_lsb0, lv and fv are sampled. setup and hold timing for the reset_bar signal with respect to d out _lsb0, lv, and fv are shown in figure 38 and table 30. these signals are sampled once by the on-chip firmware, which yields a long t hold time. figure 43. configuration timing t setup t hold valid data reset_bar line_valid table 33. configuration timing signal parameter min typ max units d out _lsb0, frame_valid, line_valid t setup 0 s t hold 50 s 1. table data is based on extclk = 27 mhz. figure 44. power up sequence vdd (1.8) vaa_pix vaa (2.8) vdd_pll vdd_dac (2.8) extclk reset_bar v dd_io (2.8) t3 t4 t5 t0 t1 hard reset internal initialization patch config spi or host streaming t2 table 34. power up sequence definition symbol min typical max unit v dd _pll to v aa /v aa _pix t0 0 ? ? ms v aa /v aa _pix to v dd _io t1 0 ? ? ms
asx340at www.onsemi.com 42 table 34. power up sequence (continued) definition unit max typical min symbol v dd _io to v dd t2 0 ? ? ms hard reset t3 2 ? ? ms internal initialization t4 14 ? ? ms 1. delay between vdd and extclk depends on customer devices, i.e. xtal, oscillator, and so on. there is no requirement on this f rom the sensor. 2. hard reset time is the minimum time required after power rails are settled. ten clock cycles are required for the sensor itse lf, assuming all power rails are settled. in a circuit where hard reset is performed by the rc circuit, then the rc time must include the all po wer rail settle time and xtal. 3. the time for patch config spi or host, that is, t5, depends on the patches being applied. figure 45. power down sequence v dd (1.8) v aa (2.8) v dd _dac (2.8) extclk v dd _io (2.8) t3 t0 t2 t1 power down until next power up cycle table 35. power down sequence definition symbol min typical max unit v dd to v dd _io t0 0 ? ? ms v dd _io to v aa /v aa _pix t1 0 ? ? ms v aa /v aa _pix to v dd _pll/dac t2 0 ? ? ms power down until next power up time t3 100 1 ? ? ms (1) t3 is required between power down and next power up time, all decoupling caps from regulators must completely discharge before next power up. figure 46. frame_sync to frame_valid/line_valid frame_sync frame_valid line_valid t frame_sync t frmsynh_fvh
asx340at www.onsemi.com 43 table 36. frame_sync to frame_valid/line_valid parameters parameter name conditions min typical max unit frame_sync to fv/lv t frmsync_fvh interlaced mode 1.22 ? ? ms t frame_sync t framesync 1 ms figure 47. reset to spi access delay reset_bar t rsth_csl spi_cs_n figure 48. reset to serial access delay reset_bar sdata t rsth_sdatal figure 49. reset to ae/awb image first frame overlay from flash reset_bar video t rsth_fvl t rsth_ovl t rsth_aeawb ae/awb settled table 37. reset_bar delay parameters parameter name conditions min typical max unit reset_bar high to spi_cs_n low trsth_csl 13 ? ? ms reset_bar high to s data low trsth_sdatal 18 ? ? ms reset_bar high to frame_valid trsth_fvl 14 ? ? ms reset_bar high to first overlay trsth_ovl overlay size dependent ? ? ? ms reset_bar high to ae/awb settled trsth_aeawb scene dependent ? ? ? ms
asx340at www.onsemi.com 44 table 37. reset_bar delay parameters (continued) parameter unit max typical min conditions name reset_bar high to first ntsc frame trsth_ntsc 47 ? ? ms reset_bar high to first pal frame trsth_pal 53 ? ? ms electrical specifications figure 50. spi output timing t su spi_cs_n spi_sclk spi_sdi spi_sdo t cs_sclk t sclk_sdo table 38. spi data setup and hold timing parameter name conditions min typical max f spi_sclk spi_sclk frequency 1.6875 4.5 18 mhz t spi_sclk spi_sclk period 55.556 592.593 ns t su setup time 0.5 * t spi_sclk ns t sclk_sdo hold time 0.5 * t spi_sclk + 20 ns t cs_sclk delay from falling edge of spi_cs_n to rising edge of spi_sclk 230 ns caution: stresses greater than those listed in table 37 may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 39. absolute maximum ratings symbol parameter rating unit min max v dd digital power (1.8 v) ? 0.3 2.4 v v dd _io i/o power (2.8 v) ? 0.3 4 v v aa v aa analog power (2.8 v) ? 0.3 4 v v aa _pix pixel array power (2.8 v) ? 0.3 4 v v dd _pll pll power (2.8 v) ? 0.3 4 v v dd _dac dac power (2.8 v) ? 0.3 4 v v in dc input voltage ? 0.3 v dd _io+0.3 v
asx340at www.onsemi.com 45 table 39. absolute maximum ratings (continued) rating unit parameter symbol min unit max parameter symbol v out dc output voltage ? 0.3 v dd _io+0.3 v t stg storage temperature ? 50 150 c 1. ?rating? column gives the maximum and minimum values that the device can tolerate. table 40. electrical characteristics and operating conditions parameter condition min typ max unit core digital voltage (v dd ) ? 1.70 1.8 1.95 v io digital voltage (v dd _io) ? 2.66 2.8 2.94 v video dac voltage (v dd_ dac) ? 2.66 2.8 2.94 v pll voltage (v dd _pll) ? 2.66 2.8 2.94 v analog voltage (v aa ) ? 2.66 2.8 2.94 v pixel supply voltage (v aa_ pix) ? 2.66 2.8 2.94 v imager operating temperature 2 ? ?40 +105 c functional operating temperature 3 ?40 +85 c storage temperature ? ?50 +150 c 1. v aa and v aa ? _pix must all be at the same potential to avoid excessive current draw. care must be taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together. 2. the imager operates in this temperature range, but image quality may degrade if it operates beyond the functional operating t emperature range. 3. image quality is not guaranteed at temperatures equal to or greater than this range. table 41. video dac electrical characteristics?single-ended mode ( f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v) parameter condition min typ max unit resolution ? 10 ? bits dnl ? 0.2 0.4 bits inl ? 0.7 3.5 bits output local load output pad (dac_pos) ? 37.5 ? w unused output (dac_neg) ? 37.5 ? w output voltage single-ended mode, code 000h ? .021 ? v single-ended mode, code 3ffh ? 1.392 ? v output current single-ended mode, code 000h ? 0.560 ? ma single-ended mode, code 3ffh ? 37.120 ? ma supply current estimate ? ? 25.0 ma dac_ref dac reference ? 1.200 ? v r dac_ref dac reference ? 2.4 ? kw 1. dac_pos, dac_neg, and dac_ref are loaded with resistors to simulate video output driving into a low pass filter and achieve a full outpu t swing of 1.4v. their resistor loadings may be different from the loadings in a real single-ended or dif ferential-ended video output system with an actual receiving end. please refer to the developer guide for proper resistor loadings.
asx340at www.onsemi.com 46 table 42. video dac electrical characteristics?differential mode ( f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v) parameter condition min typ max unit dnl ? 0.2 0.4 bits inl ? 0.7 3.5 bits output local load differential mode per pad (dac_pos and dac_neg) ? 37.5 ? output voltage differential mode, code 000h, pad dacp ? .022 ? v differential mode, code 000h, pad dacn ? 1.421 ? v differential mode, code 3ffh, pad dacp ? 1.421 ? v differential mode, code 3ffh, pad dacn ? .022 ? v output current differential mode, code 000h, pad dacp ? .587 ? ma differential mode, code 000h, pad dacn ? 37.893 ? ma differential mode, code 3ffh, pad dacp ? 37.893 ? ma differential mode, code 3ffh, pad dacn ? .587 ? ma supply current estimate ? ? 50 ma dac_ref dac reference ? 1.2 v r dac_ref dac reference 2.4 k 1. dac_pos, dac_neg, and dac_ref are loaded with resistors to simulate video output driving into a low pass filter and achieve a full outpu t swing of 1.4 v. their resistor loadings may be different from the loadings in a real single-ended or differential-ended video o utput system with an actual receiving end. please refer to the developer guide for proper resistor loadings. table 43. digital i/o parameters (t a = ambient = 25 c; all supplies at 2.8 v) signal parameter definition condition min typ max unit all outputs load capacitance 5 ? 30 pf v oh output high voltage 0.7 * v dd _io ? v v ol output low voltage ? ? 0.3* v dd _io v i oh output high current v oh = v dd _io ? 0.4 v 20 ? 35 ma i ol output low current v ol = 0.4 v 29 ? 53 ma all inputs v ih input high voltage 0.7 * v dd _io ? v dd _io + 0.5 v v il input low voltage ?0.3 ? 0.3 * v dd _io v i ih input high leakage current 0.02 ? 0.26 ma i il input low leakage current 0.01 ? 0.05 ma signal cap input signal capacitance ? 6.5 ? pf 1. all inputs are protected and may be active when all supplies (2.8 v and 1.8 v) are turned off. power consumption, operating mode table 44. power consumption ? condition 1 (extclk = 27 mhz; t = 25 c, dark condition (lens with cover)) power plane supply condition 1 typ power max power unit v dd 1.8 48.2 72 mw v dd _io 2.8 parallel off 2.2 10 mw v aa 2.8 96 140 mw vaa_pix 2.8 2.2 5 mw
asx340at www.onsemi.com 47 table 44. power consumption ? condition 1 (continued) (extclk = 27 mhz; t = 25 c, dark condition (lens with cover)) power plane unit max power typ power condition 1 supply v dd _dac 2.8 single 75w 122.9 146 mw v dd _pll 2.8 18.8 25 mw total 290.3 398 mw analog output uses single-ended mode: dac_pos = 75 , dac_neg = 37.5 , dac_ref = 2.4 k , parallel output is disabled. table 45. power consumption ? condition 2 ( f extclk = 27 mhz; t = 25 c, dark condition (lens with cover), c load = 40pf) power plane supply condition 1 typ power max power unit v dd 1.8 47.5 72 mw v dd _io 2.8 parallel on 26.6 50 mw v aa 2.8 95.5 140 mw vaa_pix 2.8 2.2 5 mw v dd _dac 2.8 vdac off 1.1 5 mw v dd _pll 2.8 18.8 25 mw total 191.7 297 mw analog output is disabled; parallel output is enabled. video signal parameters table 46. key video signal parameter table ( f extclk = 27 mhz; v dd = 1.8 v; v dd_ io = 2.8 v; v aa = 2.8 v; v aa_ pix = 2.8 v; v dd_ pll = 2.8 v; v dd _dac = 2.8 v) parameter ntsc pal units notes number of lines per frame 525 625 hz line frequency 15734.264 15625 hz field frequency 59.94 50 hz sync level 40 43 ire 2, 3 burst level 40 43 ire 2, 3 black level 7.5 0 ire 1, 2, 3 white level 100 100 ire 1, 2, 3 1. black and white levels are referenced to the blanking level. 2. 1 ire ~ 7.14 mv 3. dac ref = 2.8 kohm; load = 37.5 ohm 4. reference to itu ? r bt.470 ? 6
asx340at www.onsemi.com 48 h f a h de b c g figure 51. video timing table 47. video timing: specification from rec. itu-r bt.470-6 parameter signal ntsc (27 mhz) pal (27 mhz) units a h period 63.556 64.00 ms b hsync to burst 4.71 to 5.71 5.60 0.10 ms c burst 2.23 to 3.11 2.25 0.23 ms d hsync to signal 9.20 to 10.30 10.20 0.30 ms e video signal 52.655 0.20 52 +0, ? 0.3 ms f front 1.27 to 2.22 1.5 +0.3, ? 0.0 ms g hsync period 4.70 0.10 4.70 0.20 ms h sync rising/falling edge 3 0.25 0.20 0.10 ms
asx340at www.onsemi.com 49 figure 52. equalizing pulse l j i k k table 48. equalizing pulse: specifica tion from rec. itu-r bt.470 ? 6 parameter signal ntsc (27 mhz) pal (27 mhz) units i h/2 period 31.778 32.00 ms j pulse width 2.30 0.10 2.35 0.10 ms k pulse rising/falling edge 30.25 0.25 0.05 ms l signal to pulse 1.50 ? 0.10 3.0 2.0 ms
asx340at www.onsemi.com 50 figure 53. v pulse n m o p p table 49. v pulse: specification from rec. itu-r bt.470-6 parameter signal ntsc (27 mhz) pal (27 mhz) units m h/2 period 31.778 32.00 ms n pulse width 27.10 (nominal) 27.30 0.10 ms o v pulse interval 4.70 0.10 4.70 0.10 ms p pulse rising/falling edge 30.25 0.25 0.05 ms two-wire serial bus timing figure 49 and table 48 describe the timing for the two-wire serial interface. figure 54. two-wire serial bus timing parameters s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta table 50. two-wire serial bus characteristics (f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v; t a = 25 c) parameter symbol standard mode fast mode units min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition.
asx340at www.onsemi.com 51 table 50. two-wire serial bus characteristics (f extclk = 27 mhz; v dd = 1.8 v; v dd _io = 2.8 v; v aa = 2.8 v; v aa _pix = 2.8 v; v dd _pll = 2.8 v; v dd _dac = 2.8 v; t a = 25 c) parameter units fast mode standard mode symbol parameter units max min max min symbol after this period, the first clock pulse is generated t hd;sta 4.0 ? 0.6 ? ms low period of the s clk clock t low 4.7 ? 1.3 ? ms high period of the s clk clock t high 4.0 ? 0.6 ? ms se-up time for a repeated start condition t su;sta 4.7 ? 0.6 ? ms data hold time t hd;dat 0 4 3.45 5 0 6 0.9 5 ms data set-up time t su;dat 250 ? 100 6 ? ns rise time of both s data and s clk signals t r ? 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f ? 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 ? 0.6 ? ms bus free time between a stop and start condition t buf 4.7 ? 1.3 ? ms capacitive load for each bus line c b ? 400 ? 400 pf serial interface input pin capacitance c in_si ? 3.3 ? 3.3 pf s data max load capacitance c load_sd ? 30 ? 30 pf s data pull-up resistor r sd 1.5 4.7 1.5 4.7 kw 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf.
asx340at www.onsemi.com 52 spectral characteristics figure 55. quantum efficiency 0 10 20 30 40 50 60 70 350 450 550 650 750 850 950 1050 quantum efficiency (%) wavelength (nm) red green blue note: the measurements were done on packaged parts with regular glass coating (that is, without anti-reflective glass (arc) coating) .
asx340at www.onsemi.com 53 package dimensions case 503ae issue o ibga63 7.5 x 7.5
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